In digital communications a Cyclic Redundancy Check [CRC] is an error detecting code that are used to protect a number of given bits similar to concept of parity bit.
I have included a diagram of block diagram that aims to calculate the CRC specific to input bits $m_0 m_1\cdots m_{33}$.
In the book that I have been using the following sentence and example are provided
Bits are then passed sequentially through the exclusive-or operation (
XOR) at the input. When the last bit has entered, the output is generated by shifting the bits out of the shift register,c7first, through an inverter
As an example,
If bits $\{m_0 \ldots m_{33}\}$ are given by $\{1111000100100110000000001110000000\}$, the resulting CRC bits{c7. . .c0}are{10101000}.
Can anyone please explain to be how they mathematically obtain the 8 bits?
i. e. what are the actual operations, because I can't tell much from the figure itself.