Have a look at the above figure. I am confused in how the output bits are calculated. e.g. according to my understanding a state transition from 00 to 10 (with input bit 1) should produce output 10 instead of 11 as given in the figure. What am I doing wrong here?
Note: D is the delay element. + operation is modulo-2 addition (xor).
The output pair (Ck1, Ck2) is given by (Bk + Bk-2, Bk + Bk-1 + Bk-2). The state is given by (Bk-1, Bk-2). So, when you are at state (0,0), Bk-1 = Bk-2 = 0. Given that Bk is 1, (Ck1, Ck2) is equal to (1+0, 1+0+0) = (1,1). The new state is (1,0) because Bk-1 will become what Bk was and Bk-2 will become what Bk-1 was. I hope it helps!