As suggested in the title, I'm unhappy with the notion of circuit width I've been given in my computational complexity class. It was motivated as a model of amount of memory needed for the algorithm, but seems to me to be an arbitrary restriction.
Concretely, we define a circuit as a directed acyclic graph with inputs of in-degree 0 and AND, OR, NOT gates of in-degree 2,2,1 respectively. Given values for the inputs, one can compute values for the various gates in the obvious way and end up with some output.
The circuit width is then defined as the size of the largest antichain, not including input vertices, in the associated poset. This might seem sensible at first - if one thinks about the circuit as being partitioned into "levels" then to compute the i+1'th level one only needs the values in the i'th level, so the size of the largest level seems like a good notion for the amount of memory.
However, consider the question of finding a bounded width circuit for computing the parity function. As ever, this refers to a family of circuits, each having its width bounded by some fixed $w$, the $n$'th of which deals with inputs of size $n$.
Building circuits which intuitively need bounded memory is then simple - all one needs to remember from the first $i$ indices is the parity of their sum, so apart from remembering the inputs one only needs to keep the values of at most 5 gates at a time in their memory. But the circuit width is then unbounded, since the green vertices form an antichain. (see image below)
Am I wrong in thinking this makes width a bad measure of memory? It's worth mentioning that I can't even think of a bounded width circuit for the parity function, so perhaps an example of that might help convince me that it was my idea for circuits that was bad, not the notion itself.
I found a way of doing the parity function - instead of writing $a\oplus b$ as $(a\wedge\neg b)\vee(b\wedge\neg a)$, one can use $(a\vee b)\wedge\neg(a\wedge b)$, thus avoiding the $\neg$'s right at the start which form the pesky antichain. I think something like this can probably be done in general to make the memory intuition align more closely with the circuit width.