I have come across an interesting problem that is kind of boggling my mind: It's about implementing a 6-bit XOR or even/odd parity with as few logic gates as possible.
Obviously this would mean calculating Z = ((A XOR B) XOR (C XOR D)) XOR (E XOR F).
The caveat is that this should be done with NO xor gates, so only AND/OR/NOT. I'm trying to get this down to as few of these gates as possible, and I have a solution that needs 13 gates so far (not counting NOT):
X1 = (ABC + !A!BC + !AB!C + A!B!C)
X2 = (DEF + !D!EF + !DE!F + D!E!F)
Z = (X1 + X2) !(X1 X2)
However, supposedly this is possible with only 12 gates (again, not counting NOT). I feel like I'm missing some rather obvious boolean algebra optimization step here (not my strong suit), is there something I can reduce here?
EDIT: I'm ok with using n-bit OR/AND gates, e.g. X1 uses only 1 OR gate.
Figured out how to do it:
So basically I switched to using CNF instead of DNF, and to using the 4-NAND XOR for combining them. This way I can combine AND gates.