Consider a dual core processor which operates using a cache memory. Two processes cannot simultaneously access the cache i.e. if a process is accessing the cache and another process tries to access it, there is a conflict and the latter must wait for the former to finish accessing. Assume one process is running on each of the two cores and the probabilities of accessing the cache in any time slot are p1 and p2 respectively for the two processes. Also, the time spent to fetch the cache contents is exactly one time slot. You can assume that all requests made are independent of each other and no more retrieval requests can be generated by a process if a previous request is yet to be completed. Model the above system using a DTMC and give the transition matrix.
How do I approach this problem? I am unsure of what the states should be.