Suppose you want to construct an FSM containing one input and one output. Consider the example: The machine should assert the input (set to 1) when the last four bits taken in as input match the sequence 1011. Thus, for example, for the sequence 1011011, the FSM should assert the input twice.
How can I achieve this result using the least number of states? How would one logically think about this problem and solve it? Particularly, how does one "assert the input." That is, how does one set it equal to 1?
Try the following: The nodes are labeled with state-name/output-value and the edges with input-value. The state names are suggestive of the relevant inputs seen so far.